交通控制器eda课程设计

㈠ EDA技术课程设计———交通灯控制器

图书馆有书啊

㈡ 用EDA设计交通灯控制器的设计

ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity top_traffic is
port( clock : in std_logic;
reset : in std_logic;
chip1 : in std_logic;
chip2 : in std_logic;
seg_out : out std_logic_vector(6 downto 0);
chip_sel : out std_logic;
chip_sel1 : out std_logic;
chip_sel2 : out std_logic;
q_out : out std_logic_vector(11 downto 0)
);
end ;
architecture bhv of top_traffic is
component qhz_any
port( clk: in std_logic;
Q: out std_logic
);
end component;
component qhz_any1
port( clk: in std_logic;
Q: out std_logic
);
end component;

component mux21a
port( s : in std_logic;
a,b : in std_logic_vector(6 downto 0);
y : out std_logic_vector(6 downto 0)
);
end component;
component traffic
port( clk : in std_logic;
rst : in std_logic;
times : out integer range 0 to 100;
q : out std_logic_vector(11 downto 0);
shi: out std_logic_vector(6 downto 0);
ge: out std_logic_vector(6 downto 0)
);
end component;
signal m1 : std_logic;
signal m2 : std_logic;
signal m3 : integer range 0 to 100;
signal m4 : std_logic_vector(6 downto 0);
signal m5 : std_logic_vector(6 downto 0);
begin
u1 : qhz_any port map(clk=>clock,Q=>m1);
u2 : qhz_any1 port map(clk=>clock,Q=>m2);
u3 : qhz_any1 port map(clk=>clock,Q=>chip_sel);
u4 : traffic port map(clk=>m1,times=>m3,q=>q_out,rst=>reset,ge=>m4,shi=>m5);

u5 : mux21a port map(a=>m4,b=>m5,y=>seg_out,s=>m2);
chip_sel1<=chip1;
chip_sel2<=chip2;
end bhv;

-------------miao fenpin-----------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity qhz_any is
generic(n:integer:=20000000);
port( clk: in std_logic;
Q: out std_logic);
end qhz_any;
architecture bhv of qhz_any is
begin
process(clk)
variable cout:integer:=0;
begin
if clk'event and clk='1' then

if cout<(n/2) then
Q<='1'; cout:=cout+1;
elsif cout<(n-1) then
Q<='0'; cout:=cout+1;
else cout:=0;

end if;
end if;

end process;

end bhv;
----------------scan fenpin-----------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity qhz_any1 is
generic(n:integer:=200000);
port( clk: in std_logic;
Q: out std_logic);
end qhz_any1;
architecture bhv of qhz_any1 is
begin
process(clk)
variable cout:integer:=0;
begin
if clk'event and clk='1' then

if cout<(n/2) then
Q<='1'; cout:=cout+1;
elsif cout<(n-1) then
Q<='0'; cout:=cout+1;
else cout:=0;

end if;
end if;

end process;

end bhv;

--------------------traffic-------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity traffic is
port( clk : in std_logic;
rst : in std_logic;
times : out integer range 0 to 100;
q : out std_logic_vector(11 downto 0);
shi,ge:out std_logic_vector(6 downto 0));
end traffic;
architecture bhv of traffic is
signal cnt : integer range 0 to 100;
signal l1,l2:integer range 0 to 9;

type state_value is (s1,s2,s3,s4);
signal state : state_value;
begin
process(clk,rst)
begin
if rst='1' then
state<=s1; --S,N travel E,W stop
cnt<=39;
q<="100001100001";

elsif rising_edge(clk) then
case state is
when s1=> --s1
if cnt=0 then
state<=s2;
q<="100010100010";
cnt<=4;

else
state<=s1;
cnt<=cnt-1;
end if;
when s2=> --s2
if cnt=0 then
state<=s3;
q<="001100001100";
cnt<=44;

else
state<=s2;
cnt<=cnt-1;
end if;
when s3=> --s3
if cnt=0 then
state<=s4;
q<="010100010100";
cnt<=4;

else
state<=s3;
cnt<=cnt-1;
end if;
when s4=> --s4
if cnt=0 then
state<=s1;
q<="100001100001";
cnt<=39;

else
state<=s4;
cnt<=cnt-1;
end if;
end case;
end if;

end process;
l1<=cnt/10; l2<=cnt rem 10;---- JI SUAN SHI WEI ; GE WEI
process(l1)
begin
case l1 is ------- XIAN SHI SHI WEI
when 0=>shi<="1111110"; --0
when 1=>shi<="0110000"; --1
when 2=>shi<="1101101"; --2
when 3=>shi<="1111001"; --3
when 4=>shi<="0110011"; --4
when 5=>shi<="1011011"; --5
when 6=>shi<="1011111"; --6
when 7=>shi<="1110000"; --7
when 8=>shi<="1111111"; --8
when 9=>shi<="1111011"; --9
end case;
end process;
process(l2)
begin
case l2 is -------- XIAN SHI GE WEI
when 0=>ge<="1111110"; --0
when 1=>ge<="0110000"; --1
when 2=>ge<="1101101"; --2
when 3=>ge<="1111001"; --3
when 4=>ge<="0110011"; --4
when 5=>ge<="1011011"; --5
when 6=>ge<="1011111"; --6
when 7=>ge<="1110000"; --7
when 8=>ge<="1111111"; --8
when 9=>ge<="1111011"; --9
end case;
end process;
end bhv;
---------------------------2 xuan 1-----------
library ieee;
use ieee.std_logic_1164.all;
entity mux21a is
port( s : in std_logic;
a,b : in std_logic_vector(6 downto 0);
y : out std_logic_vector(6 downto 0)
);
end mux21a;
architecture one of mux21a is
begin
process(a,b,s)
begin
if s='0' then y<=a; else y<=b;
end if;
end process;
end one;
~~自己用过的，时间根据你的改过了，11点就熄灯，没时间写特殊情况了，自己先看看哦

㈢ 课程设计EDA交通信号灯

PLC的我有,这个还真没得

㈣ EDA课程设计

用单片机或者存储器.
如果不允许用，可以这样，整个过程分成24步，每步0.5秒。用几回个个4017计数器，完成计答数，然后用二极管矩阵完成译码,而且单片机的I/O就有锁存功能一般不用加,你可以用164来扩展I/O口,他也可以锁存的,宏晶的网站上有参考的电路图,你可以去看看.

㈤ EDA 交通控制器的设计

一、JTDKZ
假设4种状态分别为：A、B、C、D，在CLK上升沿来时，根据SB、SM状态判断交通处于何种状态，该状态输出什么信号。
设计的原理图模块：

设计源程序：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY JTDKZ IS
PORT(CLK,SM,SB:IN STD_LOGIC;
MR,MY0,MG0,BR,BY0,BG0:OUT STD_LOGIC);
END ENTITY JTDKZ;
ARCHITECTURE ART OF JTDKZ IS
TYPE STATE_TYPE IS(A,B,C,D);
SIGNAL STATE:STATE_TYPE;
BEGIN
CNT:PROCESS(CLK)IS
VARIABLE S:INTEGER RANGE 0 TO 45;
VARIABLE CLR,EN:BIT;
BEGIN
IF(CLK'EVENT AND CLK='1')THEN
IF CLR='0'THEN S:=0;
ELSIF EN='0'THEN S:=S;
ELSE S:=S+1;
END IF;
CASE STATE IS
WHEN A=>MR<='0';MY0<='0';MG0<='1';BR<='1';BY0<='0';BG0<='0';
IF(SB AND SM)='1' THEN
IF S=45 THEN STATE<=B;CLR:='0';EN:='0';
ELSE STATE<=A;CLR:='1';EN:='1';
END IF;
ELSIF(SB AND(NOT SM))='1'THEN STATE<=B;CLR:='0';EN:='0';
ELSE STATE<=A;CLR:='1';EN:='1';
END IF;
WHEN B=>MR<='0';MY0<='1';MG0<='0';BR<='1';BY0<='0';BG0<='0';
IF S=5 THEN STATE<=C;CLR:='0';EN:='0';
ELSE STATE<=B;CLR:='1';EN:='1';
END IF;
WHEN C=>MR<='1';MY0<='0';MG0<='0';BR<='0';BY0<='0';BG0<='1';
IF(SM AND SB)='1'THEN
IF S=25 THEN STATE<=D;CLR:='0';EN:='0';
ELSE STATE<=C;CLR:='1';EN:='1';
END IF;
ELSIF SB='0' THEN STATE<=D;CLR:='0';EN:='0';
ELSE STATE<=C;CLR:='1';EN:='1';
END IF;
WHEN D=>MR<='1';MY0<='0';MG0<='0';BR<='0';BY0<='1';BG0<='0';
IF S=5 THEN STATE<=A;CLR:='0';EN:='0';
ELSE STATE<=D;CLR:='1';EN:='1';
END IF;
END CASE;
END IF;
END PROCESS CNT;
END ARCHITECTURE ART;
设计仿真的截图：

二、XSKZ
根据EN45、EN25、EN05M、EN05B的信号以及3个倒计时计数器的计数状态决定输出3个倒计时计数器中某个的状态输出。
原理图模块：

设计源程序：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY XSKZ IS
PORT(EN45,EN25,EN05M,EN05B: IN STD_LOGIC;
AIN45M,AIN45B,AIN25M,AIN25B,AIN05: IN STD_LOGIC_VECTOR(7 downto 0);
DOUTB,DOUTM: OUT STD_LOGIC_VECTOR(7 downto 0));
END ENTITY XSKZ;
ARCHITECTURE ART OF XSKZ IS
SIGNAL A :STD_LOGIC_VECTOR (3 DOWNTO 0);
begin
A<= EN45&EN25&EN05M&EN05B;
PROCESS(A) IS
BEGIN
CASE A IS
WHEN"1000"=>DOUTM<=AIN45M;DOUTB<=AIN45B;
WHEN"1010"=>DOUTM<=AIN05;DOUTB<=AIN05;
WHEN"0100"=>DOUTM<=AIN25M;DOUTB<=AIN25B;
WHEN"0101"=>DOUTM<=AIN05;DOUTB<=AIN05;
WHEN OTHERS=>DOUTM<="00000000";DOUTB<="00000000";
END CASE ;
END PROCESS;
END ARCHITECTURE ART;设计仿真的截图：

三、CNT45S
CLK上升沿到来时，若到计时使能信号和SB信号有效，CNT45S开始计数，并将输入状态通过DOUT45M、DOUT45B分别输出到主、支干道显示。
设计的原理图模块：

设计源程序：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT45S IS
PORT(SB,CLK,EN45:IN STD_LOGIC;
DOUT45M,DOUT45B:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END CNT45S;
ARCHITECTURE ART OF CNT45S IS
SIGNAL CNT6B:STD_LOGIC_VECTOR(5 DOWNTO 0);
BEGIN
PROCESS(SB,CLK,EN45) IS
BEGIN
IF SB='0' THEN CNT6B<=CNT6B-CNT6B-1;
ELSIF(CLK'EVENT AND CLK='1')THEN
IF EN45='1'THEN CNT6B<=CNT6B+1;
ELSIF EN45='0'THEN CNT6B<=CNT6B-CNT6B-1;
END IF;
END IF;
END PROCESS;
PROCESS(CNT6B)IS
BEGIN
CASE CNT6B IS
WHEN"000000"=>DOUT45M<="01000101";DOUT45B<="01010000";
WHEN"000001"=>DOUT45M<="01000100";DOUT45B<="01001001";
WHEN"000010"=>DOUT45M<="01000011";DOUT45B<="01001000";
WHEN"000011"=>DOUT45M<="01000010";DOUT45B<="01000111";
WHEN"000100"=>DOUT45M<="01000001";DOUT45B<="01000110";
WHEN"000101"=>DOUT45M<="01000000";DOUT45B<="01000101";
WHEN"000110"=>DOUT45M<="00111001";DOUT45B<="01000100";
WHEN"000111"=>DOUT45M<="00111000";DOUT45B<="01000011";
WHEN"001000"=>DOUT45M<="00110111";DOUT45B<="01000010";
WHEN"001001"=>DOUT45M<="00110110";DOUT45B<="01000001";
WHEN"001010"=>DOUT45M<="00110101";DOUT45B<="01000000";
WHEN"001011"=>DOUT45M<="00110100";DOUT45B<="00111001";
WHEN"001100"=>DOUT45M<="00110011";DOUT45B<="00111000";
WHEN"001101"=>DOUT45M<="00110010";DOUT45B<="00110111";
WHEN"001110"=>DOUT45M<="00110001";DOUT45B<="00110110";
WHEN"001111"=>DOUT45M<="00110000";DOUT45B<="00110101";
WHEN"010000"=>DOUT45M<="00101001";DOUT45B<="00110100";
WHEN"010001"=>DOUT45M<="00101000";DOUT45B<="00110011";
WHEN"010010"=>DOUT45M<="00100111";DOUT45B<="00110010";
WHEN"010011"=>DOUT45M<="00100110";DOUT45B<="00110001";
WHEN"010100"=>DOUT45M<="00100101";DOUT45B<="00110000";
WHEN"010101"=>DOUT45M<="00100100";DOUT45B<="00101001";
WHEN"010110"=>DOUT45M<="00100011";DOUT45B<="00101000";
WHEN"010111"=>DOUT45M<="00100010";DOUT45B<="00100111";
WHEN"011000"=>DOUT45M<="00100001";DOUT45B<="00100110";
WHEN"011001"=>DOUT45M<="00100000";DOUT45B<="00100101";
WHEN"011010"=>DOUT45M<="00011001";DOUT45B<="00100100";
WHEN"011011"=>DOUT45M<="00011000";DOUT45B<="00100011";
WHEN"011100"=>DOUT45M<="00010111";DOUT45B<="00100010";
WHEN"011101"=>DOUT45M<="00010110";DOUT45B<="00100001";
WHEN"011110"=>DOUT45M<="00010101";DOUT45B<="00100000";
WHEN"011111"=>DOUT45M<="00010100";DOUT45B<="00011001";
WHEN"100000"=>DOUT45M<="00010011";DOUT45B<="00011000";
WHEN"100001"=>DOUT45M<="00010010";DOUT45B<="00010111";
WHEN"100010"=>DOUT45M<="00010001";DOUT45B<="00010110";
WHEN"100011"=>DOUT45M<="00010000";DOUT45B<="00010101";
WHEN"100100"=>DOUT45M<="00001001";DOUT45B<="00010100";
WHEN"100101"=>DOUT45M<="00001000";DOUT45B<="00010011";
WHEN"100110"=>DOUT45M<="00000111";DOUT45B<="00010010";
WHEN"100111"=>DOUT45M<="00000110";DOUT45B<="00010001";
WHEN"101000"=>DOUT45M<="00000101";DOUT45B<="00010000";
WHEN"101001"=>DOUT45M<="00000100";DOUT45B<="00001001";
WHEN"101010"=>DOUT45M<="00000011";DOUT45B<="00001000";
WHEN"101011"=>DOUT45M<="00000010";DOUT45B<="00000111";
WHEN"101100"=>DOUT45M<="00000001";DOUT45B<="00000110";
WHEN OTHERS=>DOUT45M<="00000000";DOUT45B<="00000000";
END CASE;
END PROCESS;
END;

设计仿真的截图：

4、CNT25S
CLK上升沿到来时，若到计时使能信号、SM信号和SB信号有效，CNT25S开始计数，并将输入状态通过DOUT25M、DOUT25B分别输出到主、支干道显示。
设计的原理图模块：

设计源程序：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT25S IS
PORT(SB,SM,CLK,EN25:IN STD_LOGIC;
DOUT25M,DOUT25B:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY CNT25S;
ARCHITECTURE ART OF CNT25S IS
SIGNAL CNT5B:STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN
PROCESS(SB,SM,CLK,EN25)IS
BEGIN
IF SB='0'THEN CNT5B<=CNT5B-CNT5B-1;
ELSIF SM='0'THEN CNT5B<=CNT5B-CNT5B-1;
ELSIF(CLK'EVENT AND CLK='1')THEN
IF EN25='1'THEN CNT5B<=CNT5B+1;
ELSIF EN25='0'THEN CNT5B<=CNT5B-CNT5B-1;
END IF;
END IF;
END PROCESS;
PROCESS(CNT5B)IS
BEGIN
CASE CNT5B IS
WHEN"00000"=>DOUNT25B<="00100101";DOUT25M<="00110000";
WHEN"00001"=>DOUNT25B<="00100100";DOUT25M<="00101001";
WHEN"00010"=>DOUNT25B<="00100011";DOUT25M<="00101000";
WHEN"00011"=>DOUNT25B<="00100010";DOUT25M<="00100111";
WHEN"00100"=>DOUNT25B<="00100001";DOUT25M<="00100110";
WHEN"00101"=>DOUNT25B<="00100000";DOUT25M<="00100101";
WHEN"00110"=>DOUNT25B<="00011001";DOUT25M<="00100100";
WHEN"00111"=>DOUNT25B<="00011000";DOUT25M<="00100011";
WHEN"01000"=>DOUNT25B<="00010111";DOUT25M<="00100010";
WHEN"01001"=>DOUNT25B<="00010110";DOUT25M<="00100001";
WHEN"01010"=>DOUNT25B<="00010101";DOUT25M<="00100000";
WHEN"01011"=>DOUNT25B<="00010100";DOUT25M<="00011001";
WHEN"01100"=>DOUNT25B<="00010011";DOUT25M<="00011000";
WHEN"01101"=>DOUNT25B<="00010010";DOUT25M<="00010111";
WHEN"01110"=>DOUNT25B<="00010001";DOUT25M<="00010110";
WHEN"01111"=>DOUNT25B<="00010000";DOUT25M<="00010101";
WHEN"10000"=>DOUNT25B<="00001001";DOUT25M<="00010100";
WHEN"10001"=>DOUNT25B<="00001000";DOUT25M<="00010011";
WHEN"10010"=>DOUNT25B<="00000111";DOUT25M<="00010010";
WHEN"10011"=>DOUNT25B<="00000110";DOUT25M<="00010001";
WHEN"10100"=>DOUNT25B<="00000101";DOUT25M<="00010000";
WHEN"10101"=>DOUNT25B<="00000100";DOUT25M<="00001001";
WHEN"10110"=>DOUNT25B<="00000011";DOUT25M<="00001000";
WHEN"10111"=>DOUNT25B<="00000010";DOUT25M<="00000111";
WHEN"11000"=>DOUNT25B<="00000001";DOUT25M<="00000110";
WHEN OTHERS=>DOUNT25B<="00000000";DOUT25M<="00000000";
END CASE;
END PROCESS;
END;
设计仿真的截图：

5、CNT05S
简单思路：CLK上升沿到来时，若到计时使能信号有效，CNT25S开始计数，并将输入状态通过DOUT05输出到主、支干道显示。
设计的原理图模块：

设计源程序
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT05S IS
PORT(CLK,EN05M,EN05B:IN STD_LOGIC;
DOUT5:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END CNT05S;
ARCHITECTURE ART OF CNT05S IS
SIGNAL CNT3B:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
PROCESS(CLK,EN05M,EN05B)IS
BEGIN
IF(CLK'EVENT AND CLK='1')THEN
IF EN05M='1'THEN CNT3B<=CNT3B+1;
ELSIF EN05B='1'THEN CNT3B<=CNT3B+1;
ELSIF EN05B='0'THEN CNT3B<=CNT3B-CNT3B-1;
END IF;
END IF;
END PROCESS;
PROCESS(CNT3B)
BEGIN
CASE CNT3B IS
WHEN"000"=>DOUT5<="00000101";
WHEN"001"=>DOUT5<="00000100";
WHEN"010"=>DOUT5<="00000011";
WHEN"011"=>DOUT5<="00000010";
WHEN"100"=>DOUT5<="00000001";
WHEN OTHERS=>DOUT5<="00000000";
END CASE;
END PROCESS;
END;
设计仿真的截图：

6、YMQ
七段译码显示器，输出0～9的数据在显示屏上。
设计的原理图模块：

设计源程序
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY YMQ IS
PORT(AIN4:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUT7: OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END ENTITY YMQ;
ARCHITECTURE ART OF YMQ IS
BEGIN
PROCESS(AIN4) IS
BEGIN
CASE AIN4 IS
WHEN "0000"=>DOUT7<="0111111";
WHEN "0001"=>DOUT7<="0000110";
WHEN "0010"=>DOUT7<="1011011";
WHEN "0011"=>DOUT7<="1001111";
WHEN "0100"=>DOUT7<="1100110";
WHEN "0101"=>DOUT7<="1101101";
WHEN "0110"=>DOUT7<="1111101";
WHEN "0111"=>DOUT7<="0000111";
WHEN "1000"=>DOUT7<="1111111";
WHEN "1001"=>DOUT7<="1101111";
WHEN OTHERS=>DOUT7<="0000000";
END CASE;
END PROCESS;
END ARCHITECTURE ART;

http://dept.xgu.cn/sfzx/wlkt/shiyan12.files/frame.htm#slide0150.htm

㈥ EDA课设交通灯信号控制器接口设计

MODEL TINY MAX_N equ 34049 STACK_LENequ32 _TEXTsegment;byte public 'CODE ' org 100h _mainprocnear @:jmp@100 @43: ;out loop header movsi,6 xorcx,cx ; cmp[si],cx jnz@44 ; pushsi lodsw ; @43_5: lodsw;[si]--> ax mov[si-4],ax cmpsi,bp jbe @43_5 ; popsi addword ptr [si-2],4;[0004]+=4 decbp decbp ;cx still is 0 ;si still point to 6 @44: ;inner loop header movword ptr ax,[si] mulbx; *= i addax,cx; +=carry adcdx,0 @45: divdi ;save current digital movword ptr [si],dx ;save current digtial to buff incsi incsi movcx,ax;move carry to cx xordx,dx cmp si,bp jbe@44 or ax,ax jnz@45 @46: leabp,[si-2];calc end ime=62

㈦ 用VHDL语言设计一个交通灯，EDA课程设计

首先最简单的方法是列出真值表。写出逻辑表达式。然后根据逻辑表达式来写出vhdl程序。在编译=》仿真=》功能分析=》输出延时=》下载程序 1.设计原理
在这个实例中，我们设计一个简单的十字路口交通灯。交通灯分东西和南北两个方向，均通过数码管和指示灯指示当前的状态。设两个方向的流量相当，红灯时间45s，绿灯时间40s，黄灯时间5s.
从交通灯的工作机理来看，无论是东西方向还是南北方向，都是一个减法计数器。只不过计数时还要判断红绿灯情况，再设置计数器的模值。
下表所示为一个初始状态和4个跳变状态。交通灯工作时状态将在4个状态间循环跳变，整个交通灯则完全按照减计数器原理进行设计。
状态 当前计数值 下一个CLOCK到来时新模值
东西方向指示 南北方向指示 东西-南北方向指示 东西方向指示 南北方向指示 东西-南北方向指示
初始 0 0 45 40 红-绿
1 6 1 红-绿 5 5 红-黄
2 1 1 红-黄 40 45 绿-红
3 1 6 绿-红 5 5 黄-红
4 1 1 45 40 红-绿
2.部分程序
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity traffic is
port(clk, urgency: in std_logic;
east_west:buffer std_logic_vector(7 downto 0);--东西方向时钟计数
south_north: buffer std_logic_vector(7 downto 0); --南北方向的时钟计数
led:buffer std_logic_vector(5 downto 0)); --交通指示灯
end traffic;

architecture arch of traffic is
。。。。。。。
end arch;

3.具体设计步骤
1） 建立一个新的工程完成上面的电路设计
2） 编译电路并使用功能仿真来验证设计
3） 引脚配置，如Part I中讨论的，这些配置是确保VHDL代码中输出端口能使用PFGA芯片上连接到LEDR和LEDG的引脚。重新编译项目，并下载到FPGA芯片上。
4） 测试电路的正确性。

㈧ 关于EDA课程设计交通指示灯

这个我以前写的，是T形路口，z1,z2,z3（c1,c2,c3）分别是主路(支路)口的红黄路灯，先是支路放行20s，再是主路放行40s，红灯到路灯中间要有5s黄灯，路灯直接到黄灯，和你需要的差不多。自己看看改改就行，电路图也很简单的去网络查查

library ieee;
use ieee.std_logic_1164.all;
entity lude is
port(clk:in bit;
z1,c1,z2,c2,z3,c3:out bit);
end entity;
architecture one of lude is
begin
process(clk)
VARIABLE TEMP1: NATURAL;
begin
if(clk'event and clk='1') then
temp1:=temp1+1;
if temp1<=20 then
z1<='1';z2<='0';z3<='0';c1<='0';c2<='0';c3<='1';
elsif temp1<=25 then
z1<='0';z2<='1';z3<='0';c1<='0';c2<='0';c3<='1';
elsif temp1<=65 then
z1<='0';z2<='0';z3<='1';c1<='1';c2<='0';c3<='0';
elsif temp1<=70 then
z1<='0';z2<='0';z3<='1';c1<='0';c2<='1';c3<='0';
elsif temp1>70 then
temp1:=0;
end if;
end if;
end process;
end;

㈨ eda课程设计 地铁自动售票机控制系统的设计

地铁自动售票机控制的
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